What is a word in computer architecture

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In computing, a word is the natural unit of data used by a particular processor design. A word is a fixed-sized datum handled as a unit by the instruction set or the hardware of the processor. The number of bits or digits^[a] in a word (the word size, word width, or word length) is an important characteristic of any specific processor design or computer architecture.

The size of a word is reflected in many aspects of a computer’s structure and operation; the majority of the registers in a processor are usually word-sized and the largest datum that can be transferred to and from the working memory in a single operation is a word in many (not all) architectures. The largest possible address size, used to designate a location in memory, is typically a hardware word (here, «hardware word» means the full-sized natural word of the processor, as opposed to any other definition used).

Documentation for older computers with fixed word size commonly states memory sizes in words rather than bytes or characters. The documentation sometimes uses metric prefixes correctly, sometimes with rounding, e.g., 65 kilowords (KW) meaning for 65536 words, and sometimes uses them incorrectly, with kilowords (KW) meaning 1024 words (2¹⁰) and megawords (MW) meaning 1,048,576 words (2²⁰). With standardization on 8-bit bytes and byte addressability, stating memory sizes in bytes, kilobytes, and megabytes with powers of 1024 rather than 1000 has become the norm, although there is some use of the IEC binary prefixes.

Several of the earliest computers (and a few modern as well) use binary-coded decimal rather than plain binary, typically having a word size of 10 or 12 decimal digits, and some early decimal computers have no fixed word length at all. Early binary systems tended to use word lengths that were some multiple of 6-bits, with the 36-bit word being especially common on mainframe computers. The introduction of ASCII led to the move to systems with word lengths that were a multiple of 8-bits, with 16-bit machines being popular in the 1970s before the move to modern processors with 32 or 64 bits.^[1] Special-purpose designs like digital signal processors, may have any word length from 4 to 80 bits.^[1]

The size of a word can sometimes differ from the expected due to backward compatibility with earlier computers. If multiple compatible variations or a family of processors share a common architecture and instruction set but differ in their word sizes, their documentation and software may become notationally complex to accommodate the difference (see Size families below).

Uses of words[edit]

Depending on how a computer is organized, word-size units may be used for:

Fixed-point numbers

Holders for fixed point, usually integer, numerical values may be available in one or in several different sizes, but one of the sizes available will almost always be the word. The other sizes, if any, are likely to be multiples or fractions of the word size. The smaller sizes are normally used only for efficient use of memory; when loaded into the processor, their values usually go into a larger, word sized holder.

Floating-point numbers

Holders for floating-point numerical values are typically either a word or a multiple of a word.

Addresses

Holders for memory addresses must be of a size capable of expressing the needed range of values but not be excessively large, so often the size used is the word though it can also be a multiple or fraction of the word size.

Registers

Processor registers are designed with a size appropriate for the type of data they hold, e.g. integers, floating-point numbers, or addresses. Many computer architectures use general-purpose registers that are capable of storing data in multiple representations.

Memory–processor transfer

When the processor reads from the memory subsystem into a register or writes a register’s value to memory, the amount of data transferred is often a word. Historically, this amount of bits which could be transferred in one cycle was also called a catena in some environments (such as the Bull GAMMA 60 [fr]).^[2][3] In simple memory subsystems, the word is transferred over the memory data bus, which typically has a width of a word or half-word. In memory subsystems that use caches, the word-sized transfer is the one between the processor and the first level of cache; at lower levels of the memory hierarchy larger transfers (which are a multiple of the word size) are normally used.

Unit of address resolution

In a given architecture, successive address values designate successive units of memory; this unit is the unit of address resolution. In most computers, the unit is either a character (e.g. a byte) or a word. (A few computers have used bit resolution.) If the unit is a word, then a larger amount of memory can be accessed using an address of a given size at the cost of added complexity to access individual characters. On the other hand, if the unit is a byte, then individual characters can be addressed (i.e. selected during the memory operation).

Instructions

Machine instructions are normally the size of the architecture’s word, such as in RISC architectures, or a multiple of the «char» size that is a fraction of it. This is a natural choice since instructions and data usually share the same memory subsystem. In Harvard architectures the word sizes of instructions and data need not be related, as instructions and data are stored in different memories; for example, the processor in the 1ESS electronic telephone switch has 37-bit instructions and 23-bit data words.

Word size choice[edit]

When a computer architecture is designed, the choice of a word size is of substantial importance. There are design considerations which encourage particular bit-group sizes for particular uses (e.g. for addresses), and these considerations point to different sizes for different uses. However, considerations of economy in design strongly push for one size, or a very few sizes related by multiples or fractions (submultiples) to a primary size. That preferred size becomes the word size of the architecture.

Character size was in the past (pre-variable-sized character encoding) one of the influences on unit of address resolution and the choice of word size. Before the mid-1960s, characters were most often stored in six bits; this allowed no more than 64 characters, so the alphabet was limited to upper case. Since it is efficient in time and space to have the word size be a multiple of the character size, word sizes in this period were usually multiples of 6 bits (in binary machines). A common choice then was the 36-bit word, which is also a good size for the numeric properties of a floating point format.

After the introduction of the IBM System/360 design, which uses eight-bit characters and supports lower-case letters, the standard size of a character (or more accurately, a byte) becomes eight bits. Word sizes thereafter are naturally multiples of eight bits, with 16, 32, and 64 bits being commonly used.

Variable-word architectures[edit]

Early machine designs included some that used what is often termed a variable word length. In this type of organization, an operand has no fixed length. Depending on the machine and the instruction, the length might be denoted by a count field, by a delimiting character, or by an additional bit called, e.g., flag, or word mark. Such machines often use binary-coded decimal in 4-bit digits, or in 6-bit characters, for numbers. This class of machines includes the IBM 702, IBM 705, IBM 7080, IBM 7010, UNIVAC 1050, IBM 1401, IBM 1620, and RCA 301.

Most of these machines work on one unit of memory at a time and since each instruction or datum is several units long, each instruction takes several cycles just to access memory. These machines are often quite slow because of this. For example, instruction fetches on an IBM 1620 Model I take 8 cycles (160 μs) just to read the 12 digits of the instruction (the Model II reduced this to 6 cycles, or 4 cycles if the instruction did not need both address fields). Instruction execution takes a variable number of cycles, depending on the size of the operands.

Word, bit and byte addressing[edit]

The memory model of an architecture is strongly influenced by the word size. In particular, the resolution of a memory address, that is, the smallest unit that can be designated by an address, has often been chosen to be the word. In this approach, the word-addressable machine approach, address values which differ by one designate adjacent memory words. This is natural in machines which deal almost always in word (or multiple-word) units, and has the advantage of allowing instructions to use minimally sized fields to contain addresses, which can permit a smaller instruction size or a larger variety of instructions.

When byte processing is to be a significant part of the workload, it is usually more advantageous to use the byte, rather than the word, as the unit of address resolution. Address values which differ by one designate adjacent bytes in memory. This allows an arbitrary character within a character string to be addressed straightforwardly. A word can still be addressed, but the address to be used requires a few more bits than the word-resolution alternative. The word size needs to be an integer multiple of the character size in this organization. This addressing approach was used in the IBM 360, and has been the most common approach in machines designed since then.

When the workload involves processing fields of different sizes, it can be advantageous to address to the bit. Machines with bit addressing may have some instructions that use a programmer-defined byte size and other instructions that operate on fixed data sizes. As an example, on the IBM 7030^[4] («Stretch»), a floating point instruction can only address words while an integer arithmetic instruction can specify a field length of 1-64 bits, a byte size of 1-8 bits and an accumulator offset of 0-127 bits.

In a byte-addressable machine with storage-to-storage (SS) instructions, there are typically move instructions to copy one or multiple bytes from one arbitrary location to another. In a byte-oriented (byte-addressable) machine without SS instructions, moving a single byte from one arbitrary location to another is typically:

1. LOAD the source byte
2. STORE the result back in the target byte

Individual bytes can be accessed on a word-oriented machine in one of two ways. Bytes can be manipulated by a combination of shift and mask operations in registers. Moving a single byte from one arbitrary location to another may require the equivalent of the following:

1. LOAD the word containing the source byte
2. SHIFT the source word to align the desired byte to the correct position in the target word
3. AND the source word with a mask to zero out all but the desired bits
4. LOAD the word containing the target byte
5. AND the target word with a mask to zero out the target byte
6. OR the registers containing the source and target words to insert the source byte
7. STORE the result back in the target location

Alternatively many word-oriented machines implement byte operations with instructions using special byte pointers in registers or memory. For example, the PDP-10 byte pointer contained the size of the byte in bits (allowing different-sized bytes to be accessed), the bit position of the byte within the word, and the word address of the data. Instructions could automatically adjust the pointer to the next byte on, for example, load and deposit (store) operations.

Powers of two[edit]

Different amounts of memory are used to store data values with different degrees of precision. The commonly used sizes are usually a power of two multiple of the unit of address resolution (byte or word). Converting the index of an item in an array into the memory address offset of the item then requires only a shift operation rather than a multiplication. In some cases this relationship can also avoid the use of division operations. As a result, most modern computer designs have word sizes (and other operand sizes) that are a power of two times the size of a byte.

Size families[edit]

As computer designs have grown more complex, the central importance of a single word size to an architecture has decreased. Although more capable hardware can use a wider variety of sizes of data, market forces exert pressure to maintain backward compatibility while extending processor capability. As a result, what might have been the central word size in a fresh design has to coexist as an alternative size to the original word size in a backward compatible design. The original word size remains available in future designs, forming the basis of a size family.

In the mid-1970s, DEC designed the VAX to be a 32-bit successor of the 16-bit PDP-11. They used word for a 16-bit quantity, while longword referred to a 32-bit quantity; this terminology is the same as the terminology used for the PDP-11. This was in contrast to earlier machines, where the natural unit of addressing memory would be called a word, while a quantity that is one half a word would be called a halfword. In fitting with this scheme, a VAX quadword is 64 bits. They continued this 16-bit word/32-bit longword/64-bit quadword terminology with the 64-bit Alpha.

Another example is the x86 family, of which processors of three different word lengths (16-bit, later 32- and 64-bit) have been released, while word continues to designate a 16-bit quantity. As software is routinely ported from one word-length to the next, some APIs and documentation define or refer to an older (and thus shorter) word-length than the full word length on the CPU that software may be compiled for. Also, similar to how bytes are used for small numbers in many programs, a shorter word (16 or 32 bits) may be used in contexts where the range of a wider word is not needed (especially where this can save considerable stack space or cache memory space). For example, Microsoft’s Windows API maintains the programming language definition of WORD as 16 bits, despite the fact that the API may be used on a 32- or 64-bit x86 processor, where the standard word size would be 32 or 64 bits, respectively. Data structures containing such different sized words refer to them as:

• WORD (16 bits/2 bytes)
• DWORD (32 bits/4 bytes)
• QWORD (64 bits/8 bytes)

A similar phenomenon has developed in Intel’s x86 assembly language – because of the support for various sizes (and backward compatibility) in the instruction set, some instruction mnemonics carry «d» or «q» identifiers denoting «double-«, «quad-» or «double-quad-«, which are in terms of the architecture’s original 16-bit word size.

An example with a different word size is the IBM System/360 family. In the System/360 architecture, System/370 architecture and System/390 architecture, there are 8-bit bytes, 16-bit halfwords, 32-bit words and 64-bit doublewords. The z/Architecture, which is the 64-bit member of that architecture family, continues to refer to 16-bit halfwords, 32-bit words, and 64-bit doublewords, and additionally features 128-bit quadwords.

In general, new processors must use the same data word lengths and virtual address widths as an older processor to have binary compatibility with that older processor.

Often carefully written source code – written with source-code compatibility and software portability in mind – can be recompiled to run on a variety of processors, even ones with different data word lengths or different address widths or both.

Table of word sizes[edit]

^[8][9]

See also[edit]

• Integer (computer science)

Notes[edit]

References[edit]

Базовый блок памяти, обрабатываемый компьютером

В вычислениях, слово — это естественная единица данных, используемая конкретной конструкцией процессора . Слово — это фрагмент данных фиксированного размера, обрабатываемый как единица набором команд или аппаратными средствами процессора. Количество бит в слове (размер слова, ширина слова или длина слова) является важной характеристикой любой конкретной конструкции процессора или компьютерной архитектуры.

Размер слова отражается во многих аспектах устройства и работы компьютера; большинство регистров в процессоре обычно имеют размер слова, и самый большой фрагмент данных, который может быть передан в и из рабочей памяти за одну операцию, — это слово из многих ( не все) архитектуры. Наибольший возможный размер адреса, используемый для обозначения места в памяти, обычно является аппаратным словом (здесь «аппаратное слово» означает полноразмерное естественное слово процессора, в отличие от любого другого используемого определения).

Некоторые из самых ранних компьютеров (а также несколько современных) использовали двоично-десятичное, а не обычное двоичное, обычно с размером слова 10 или 12 десятичные цифры, а некоторые ранние десятичные компьютеры вообще не имели фиксированной длины слова. Ранние двоичные системы имели тенденцию использовать длину слова, несколько кратную 6-битному, причем 36-битное слово было особенно распространено на мэйнфреймах компьютерах. Введение ASCII привело к переходу к системам с длиной слова, кратной 8-битной, с 16-битными машинами, которые были популярны в 1970-х годах до перехода на современные процессоры с 32 или 64 битами. Конструкции специального назначения, такие как процессоры цифровых сигналов, могут иметь любую длину слова от 4 до 80 бит.

Размер слова иногда может отличаться от ожидаемого из-за обратной совместимости с более ранними компьютерами. Если несколько совместимых вариантов или семейство процессоров имеют общую архитектуру и набор инструкций, но различаются размером слов, их документация и программное обеспечение могут стать сложными в системе обозначений, чтобы учесть разницу (см. Семейства размеров ниже).

Содержание

• 1 Использование слов
• 2 Выбор размера слова
  • 2.1 Архитектура переменных слов
  • 2.2 Адресация слов и байтов
  • 2.3 Степени двух
• 3 Семейство размеров
• 4 Таблица размеров слов
• 5 См. Также
• 6 Ссылки

Использование слов

В зависимости от того, как устроен компьютер, единицы размера слова могут использоваться для:

Фиксированной точки числа

Держатели для фиксированной точки, обычно целого числа, числовые значения могут быть доступны в одном или нескольких разных размерах, но один из доступных размеров почти всегда будет слово. Другие размеры, если таковые имеются, скорее всего, будут кратны или дроби размера слова. Меньшие размеры обычно используются только для эффективного использования памяти; при загрузке в процессор их значения обычно попадают в более крупный держатель размером с слово.

Числа с плавающей запятой

Держатели для числовых значений с плавающей запятой обычно либо слово или кратное слово.

Адреса

Держатели для адресов памяти должны иметь размер, способный выражать необходимый диапазон значений, но не быть чрезмерно большим, поэтому часто используемый размер слово, хотя оно также может быть кратным или дробной части размера слова.

Регистры

Регистры процессора имеют размер, соответствующий типу данных, которые они хранят, например целые числа, числа с плавающей запятой или адреса. Многие компьютерные архитектуры используют регистры общего назначения, которые могут хранить данные в нескольких представлениях.

Передача памяти и процессора

Когда процессор считывает данные из подсистемы памяти в зарегистрировать или записать значение регистра в память, объем передаваемых данных часто выражается словом. Исторически такое количество битов, которое могло быть передано за один цикл, в некоторых средах также называлось катеной (например, Bull GAMMA 60 [fr ]). В простых подсистемах памяти слово передается по шине данных памяти, которая обычно имеет ширину слова или полуслова. В подсистемах памяти, которые используют кеши, передача размером с слово — это передача между процессором и первым уровнем кеша; на более низких уровнях иерархии памяти обычно используются более крупные передачи (кратные размеру слова).

Единица разрешения адреса

В данной архитектуре, последовательные значения адреса обозначают последовательные единицы памяти; эта единица — единица разрешения адреса. На большинстве компьютеров единицей измерения является либо символ (например, байт), либо слово. (Некоторые компьютеры использовали битовое разрешение.) Если единицей измерения является слово, то можно получить доступ к большему объему памяти, используя адрес заданного размера за счет дополнительной сложности доступа к отдельным символам. С другой стороны, если единицей измерения является байт, то можно адресовать отдельные символы (т. Е. Выбирать во время операции с памятью).

Инструкции

Машинные команды обычно имеют размер слова архитектуры, например, в архитектурах RISC, или кратное размеру «char», составляющее его долю. Это естественный выбор, поскольку инструкции и данные обычно используют одну и ту же подсистему памяти. В гарвардской архитектуре размеры слов инструкций и данных не должны быть связаны, поскольку инструкции и данные хранятся в разных запоминающих устройствах; например, процессор в электронном телефонном коммутаторе 1ESS имел 37-битные инструкции и 23-битные слова данных.

Выбор размера слова

При проектировании компьютерной архитектуры выбор размер слова имеет существенное значение. Существуют конструктивные соображения, которые поощряют определенные размеры битовых групп для конкретных целей (например, для адресов), и эти соображения указывают на разные размеры для разных целей. Однако соображения экономии при проектировании настоятельно требуют использования одного размера или очень небольшого числа размеров, связанных кратными или дробными (частичными) размерами с основным размером. Этот предпочтительный размер становится размером слова архитектуры.

Размер символа был в прошлом (кодировка символов с предварительной переменной размером ) одно из влияний на единицу разрешения адреса и выбор размера слова. До середины 1960-х символы чаще всего хранились в шести битах; это позволяло использовать не более 64 символов, поэтому алфавит был ограничен прописными буквами. Поскольку во времени и пространстве эффективно иметь размер слова, кратный размеру символа, размеры слова в этот период обычно были кратны 6 битам (в двоичных машинах). Тогда обычным выбором было 36-битное слово, которое также является хорошим размером для числовых свойств формата с плавающей запятой.

После внедрения дизайна IBM System / 360, в котором использовались восьмибитные символы и поддерживались строчные буквы, стандартный размер символа (или более точно, байт ) стал восемью битами. После этого размер слов, естественно, был кратен восьми битам, причем обычно использовались 16, 32 и 64 бит.

Архитектуры с переменной длиной слова

Ранние разработки машин включали некоторые, в которых использовалось то, что часто называют переменной длиной слова. В этом типе организации числовой операнд не имеет фиксированной длины, а его конец обнаруживается при обнаружении символа со специальной маркировкой, часто называемой словесным знаком. Такие машины часто использовали десятичные дроби с двоичным кодом для чисел. К этому классу машин относились IBM 702, IBM 705, IBM 7080, IBM 7010, UNIVAC 1050, IBM 1401 и IBM 1620.

Большинство этих машин работают с одной единицей памяти за раз, и поскольку каждая инструкция или данные имеют длину в несколько единиц, каждая инструкция занимает несколько циклов только для доступ к памяти. Из-за этого эти машины часто довольно медленные. Например, выборка инструкций в IBM 1620 Model I занимает 8 циклов только для чтения 12 цифр инструкции (Model II сократила это до 6 циклов или 4 циклов, если инструкция не нуждалась в обоих адресных полях). Выполнение инструкции занимало совершенно разное количество циклов в зависимости от размера операндов.

Адресация слов и байтов

Модель памяти в архитектуре сильно зависит от размера слова. В частности, в качестве слова часто выбирается разрешение адреса памяти, то есть наименьшая единица, которая может быть обозначена адресом. В этом подходе используется машина с адресацией по словам, значения адресов, которые отличаются на единицу, обозначают соседние слова памяти. Это естественно для машин, которые почти всегда работают с единицами слова (или нескольких слов), и имеет то преимущество, что позволяет командам использовать поля минимального размера для хранения адресов, что позволяет использовать меньший размер команды или большее разнообразие инструкций.

Когда обработка байтов должна составлять значительную часть рабочей нагрузки, обычно более выгодно использовать байт, а не слово в качестве единицы разрешения адреса. Значения адресов, которые отличаются на единицу, обозначают соседние байты в памяти. Это позволяет напрямую обращаться к произвольному символу в строке символов. Слово все еще может быть адресовано, но используемый адрес требует на несколько бит больше, чем альтернатива разрешения слова. Размер слова должен быть целым числом, кратным размеру символа в этой организации. Такой подход к адресации использовался в IBM 360 и с тех пор является наиболее распространенным подходом в машинах, разработанных.

В машине с побайтовой ориентацией (с байтовой адресацией ) перемещение одного байта из одного произвольного местоположения в другое обычно:

1. ЗАГРУЗИТЬ исходный байт
2. СОХРАНИТЕ результат обратно в целевой байт

. К отдельным байтам можно получить доступ на машине, ориентированной на слова, одним из двух способов. Байтами можно манипулировать с помощью комбинации операций сдвига и маски в регистрах. Для перемещения одного байта из одного произвольного места в другое может потребоваться эквивалент следующего:

1. ЗАГРУЗИТЬ слово, содержащее исходный байт
2. SHIFT исходное слово, чтобы выровнять желаемый байт с правильной позицией в целевом объекте слово
3. И исходное слово с маской для обнуления всех битов, кроме желаемых
4. ЗАГРУЗИТЬ слово, содержащее целевой байт
5. И целевое слово с маской до нуля из целевого байта
6. OR регистры, содержащие исходное и целевое слова, чтобы вставить исходный байт
7. СОХРАНИТЬ результат обратно в целевое местоположение

В качестве альтернативы многие машины, ориентированные на слова, реализуют байтовые операции с инструкциями, используя специальные байтовые указатели в регистрах или в памяти. Например, указатель байта PDP-10 содержал размер байта в битах (позволяющий получить доступ к байтам разного размера), битовую позицию байта в слове и адрес слова данные. Инструкции могут автоматически настраивать указатель на следующий байт, например, при операциях загрузки и депонирования (сохранения).

Степени двух

Разные объемы памяти используются для хранения значений данных с разной степенью точности. Обычно используемые размеры — это степень двух, кратных единице разрешения адреса (байту или слову). Преобразование индекса элемента в массиве в адрес элемента требует только операции shift, а не умножения. В некоторых случаях эта связь позволяет избежать использования операций деления. В результате большинство современных компьютерных разработок имеют размеры слова (и другие размеры операндов), которые в два раза превышают размер байта.

Семейства размеров

По мере того, как компьютерные конструкции становились все более сложными, центральное значение размера одного слова для архитектуры уменьшалось. Хотя более мощное оборудование может использовать более широкий спектр размеров данных, рыночные силы оказывают давление на поддержание обратной совместимости при одновременном расширении возможностей процессора. В результате то, что могло быть центральным размером слова в новом дизайне, должно сосуществовать в качестве альтернативного размера к исходному размеру слова в обратно совместимом дизайне. Исходный размер слова остается доступным в будущих проектах, формируя основу семейства размеров.

В середине 1970-х годов DEC разработал VAX как 32-битный преемник 16-битного PDP-11. Они использовали слово для 16-битной величины, а длинное слово — для 32-битной величины. Это отличалось от более ранних машин, где естественная единица адресации памяти называлась словом, а величина, равная половине слова, называлась полусловом. В соответствии с этой схемой квадраслово VAX составляет 64 бита. Они продолжили эту терминологию слова / длинного слова / четверного слова с 64-битным Alpha.

Другим примером является семейство x86, в котором процессоры трех разных длин слов (16-бит, позже 32- и 64-бит), а слово продолжает обозначать 16-битное количество. Поскольку программное обеспечение обычно переносится с одного слова на другое, некоторые API и документация определяют или ссылаются на более старую (и, следовательно, более короткую) длину слова, чем полная длина слова на ЦП, для которого может быть скомпилировано программное обеспечение. Кроме того, аналогично тому, как байты используются для небольших чисел во многих программах, более короткое слово (16 или 32 бита) может использоваться в контекстах, где диапазон более широкого слова не требуется (особенно когда это может сэкономить значительное пространство стека или кеш пространство памяти). Например, Microsoft Windows API поддерживает определение WORD в языке программирования как 16-битное, несмотря на то, что API может использоваться на 32- или 64-битном процессоре x86, где стандартный размер слова будет 32 или 64 бита соответственно. Структуры данных, содержащие слова разного размера, называют их СЛОВО (16 бит / 2 байта), DWORD (32 бита / 4 байта) и QWORD (64 бит / 8 байтов) соответственно. Похожее явление развилось в языке ассемблера Intel x86 — из-за поддержки различных размеров (и обратной совместимости) в наборе команд некоторые мнемоники команд содержат «d» или «q». «идентификаторы, обозначающие« двойное »,« четверное »или« двойное четверное », которые соответствуют исходному 16-разрядному размеру слова архитектуры.

В общем, новые процессоры должны использовать ту же длину слова данных и ширину виртуального адреса, что и старый процессор, чтобы иметь двоичную совместимость с этим старым процессором.

Часто тщательно написанный исходный код — написанный с учетом совместимости исходного кода и переносимости программного обеспечения — может быть перекомпилирован для работы на различных процессорах, даже с разными длины слова данных или разная ширина адреса или и то, и другое.

Таблица размеров слов

См. Также

• Целое число (информатика)

Ссылки

In computing, word is a term for the natural unit of data used by a particular processor design. A word is basically a fixed sized group of bits that are handled as a unit by the instruction set and/or hardware of the processor. The number of bits in a word (the word size, word width, or word length) is an important characteristic of a specific processor design or computer architecture.

The size of a word is reflected in many aspects of a computer’s structure and operation; the majority of the registers in a processor are usually word sized and the largest piece of data that can be transferred to and from the working memory in a single operation is a word in many (not all) architectures. The largest possible address size, used to designate a location in memory, is typically a hardware word (in other words, the full-sized natural word of the processor, as opposed to any other definition used).

Modern processors, including embedded systems, usually have a word size of 8, 16, 24, 32 or 64 bits, while modern general purpose computers usually use 32 or 64 bits. Special purpose digital processors, such as DSPs for instance, may use other sizes and many different sizes have been used historically, including 8, 9, 12, 18, 24, 36, 39, 40, 48 and 60 bits. The slab is an example of a system with an earlier word size. Several of the earliest computers (and a few modern as well) used BCD rather than plain binary, typically having a word size of 10 or 12 decimal digits, and some early decimal computers had no fixed word length at all.

The size of a word can sometimes differ from the expected due to backward compatibility with earlier computers. If multiple compatible variations or a family of processors share a common architecture and instruction set but differ in their word sizes, their documentation and software may become notationally complex to accommodate the difference (see Size families below).

Uses of words

Depending on how a computer is organized, units of the word size may be used for:

• Integer numbers: Holders for integer numerical values may be available in one or in several different sizes, but one of the sizes available will almost always be the word. The other sizes, if any, are likely to be multiples or fractions of the word size. The smaller sizes are normally used only for efficient use of memory; when loaded into the processor, their values usually go into a larger, word sized holder.

• Floating point numbers: Holders for floating point numerical values are typically either a word or a multiple of a word.

• Addresses: Holders for memory addresses must be of a size capable of expressing the needed range of values but not be excessively large, so often the size used is the word though it can also be a multiple or fraction of the word size.

• Registers: Processor registers are designed with a size appropriate for the type of data they hold, e.g. integers, floating point numbers or addresses. Many computer architectures use «general purpose» registers that can hold any of several types of data, these registers must be sized to hold the largest of the types, historically this is the word size of the architecture though increasingly special purpose, larger, registers have been added to deal with newer types.

• Memory-processor transfer: When the processor reads from the memory subsystem into a register or writes a register’s value to memory, the amount of data transferred is often a word. In simple memory subsystems, the word is transferred over the memory data bus, which typically has a width of a word or half-word. In memory subsystems that use caches, the word-sized transfer is the one between the processor and the first level of cache; at lower levels of the memory hierarchy larger transfers (which are a multiple of the word size) are normally used.

• Unit of address resolution: In a given architecture, successive address values designate successive units of memory; this unit is the unit of address resolution. In most computers, the unit is either a character (e.g. a byte) or a word. (A few computers have used bit resolution.) If the unit is a word, then a larger amount of memory can be accessed using an address of a given size. On the other hand, if the unit is a byte, then individual characters can be addressed (i.e. selected during the memory operation).

• Instructions: Machine instructions are normally fractions or multiples of the architecture’s word size. This is a natural choice since instructions and data usually share the same memory subsystem. In Harvard architectures the word sizes of instructions and data need not be related.

Word size choice

When a computer architecture is designed, the choice of a word size is of substantial importance. There are design considerations which encourage particular bit-group sizes for particular uses (e.g. for addresses), and these considerations point to different sizes for different uses. However, considerations of economy in design strongly push for one size, or a very few sizes related by multiples or fractions (submultiples) to a primary size. That preferred size becomes the word size of the architecture.

Character size is one of the influences on a choice of word size. Before the mid-1960s, characters were most often stored in six bits; this allowed no more than 64 characters, so alphabetics were limited to upper case. Since it is efficient in time and space to have the word size be a multiple of the character size, word sizes in this period were usually multiples of 6 bits (in binary machines). A common choice then was the 36-bit word, which is also a good size for the numeric properties of a floating point format.

After the introduction of the IBM System/360 design which used eight-bit characters and supported lower-case letters, the standard size of a character (or more accurately, a byte) became eight bits. Word sizes thereafter were naturally multiples of eight bits, with 16, 32, and 64 bits being commonly used.

Variable word architectures

Early machine designs included some that used what is often termed a variable word length. In this type of organization, a numeric operand had no fixed length but rather its end was detected when a character with a special marking was encountered. Such machines often used binary coded decimal for numbers. This class of machines included the IBM 702, IBM 705, IBM 7080, IBM 7010, UNIVAC 1050, IBM 1401, and IBM 1620.

Most of these machines work on one unit of memory at a time and since each instruction or datum is several units long, each instruction takes several cycles just to access memory. These machines are often quite slow because of this. For example, instruction fetches on an IBM 1620 Model I take 8 cycles just to read the 12 digits of the instruction (the Model II reduced this to 6 cycles, or 4 cycles if the instruction did not need both address fields). Instruction execution took a completely variable number of cycles, depending on the size of the operands.

Word and byte addressing

The memory model of an architecture is strongly influenced by the word size. In particular, the resolution of a memory address, that is, the smallest unit that can be designated by an address, has often been chosen to be the word. In this approach, address values which differ by one designate adjacent memory words. This is natural in machines which deal almost always in word (or multiple-word) units, and has the advantage of allowing instructions to use minimally-sized fields to contain addresses, which can permit a smaller instruction size or a larger variety of instructions.

When byte processing is to be a significant part of the workload, it is usually more advantageous to use the byte, rather than the word, as the unit of address resolution. This allows an arbitrary character within a character string to be addressed straightforwardly. A word can still be addressed, but the address to be used requires a few more bits than the word-resolution alternative. The word size needs to be an integral multiple of the character size in this organization. This addressing approach was used in the IBM 360, and has been the most common approach in machines designed since then.

The power of two

Different amounts of memory are used to store data values with different degrees of precision. The commonly used sizes are usually a power of two multiple of the unit of address resolution (byte or word). Converting the index of an item in an array into the address of the item then requires only a shift operation rather than a multiplication. In some cases this relationship can also avoid the use of division operations. As a result, most modern computer designs have word sizes (and other operand sizes) that are a power of two times the size of a byte.

Size families

As computer designs have grown more complex, the central importance of a single word size to an architecture has decreased. Although more capable hardware can use a wider variety of sizes of data, market forces exert pressure to maintain backward compatibility while extending processor capability. As a result, what might have been the central word size in a fresh design has to coexist as an alternative size to the original word size in a backward compatible design. The original word size remains available in future designs, forming the basis of a size family.

In the mid-1970s, DEC designed the VAX to be a successor of the PDP-11. They used word for a 16-bit quantity, while longword referred to a 32-bit quantity. This was in contrast to earlier machines, where the natural unit of addressing memory would be called a word, while a quantity that is one half a word would be called a halfword. In fitting with this scheme, a VAX quadword is 64 bits.

Another example is the x86 family, of which processors of three different word lengths (16-bit, later 32- and 64-bit) have been released. As software is routinely ported from one word-length to the next, some APIs and documentation define or refer to an older (and thus shorter) word-length than the full word length on the CPU that software may be compiled for. Also, similar to how bytes are used for small numbers in many programs, a shorter word (16 or 32 bits) may be used in contexts where the range of a wider word in not needed (especially where this can save considerable stack space or cache memory space). For example, Microsoft’s Windows API maintains the programming language definition of WORD as 16 bits, despite the fact that the API may be used on a 32- or 64-bit x86 processor, where the standard word size would be 32 or 64 bits, respectively. Data structures containing such different sized words refer to them as WORD, DWORD and QWORD respectively. A similar phenomenon has developed in Intel’s x86 assembly language – because of the support for various sizes (and backward compatibility) in the instruction set, some instruction mnemonics carry «d» or «q» identifiers denoting «double-«, «quad-» or «double-quad-«, which are in terms of the architecture’s original 16-bit word size.

Table of word sizes

^[3][4]

See also

• 32-bit
• 32-bit applications
• 64-bit
• 128-bit
• Integer
• Short integer
• Long integer

References

In computing, a word is the natural unit of data used by a particular processor design. A word is a fixed-sized datum handled as a unit by the instruction set or the hardware of the processor. The number of bits or digits in a word (the word size, word width, or word length) is an important characteristic of any specific processor design or computer architecture.

The size of a word is reflected in many aspects of a computer’s structure and operation; the majority of the registers in a processor are usually word sized and the largest datum that can be transferred to and from the working memory in a single operation is a word in many (not all) architectures. The largest possible address size, used to designate a location in memory, is typically a hardware word (here, «hardware word» means the full-sized natural word of the processor, as opposed to any other definition used).

Documentation for older computers with fixed word size commonly states memory sizes in words rather than bytes or characters. The documentation sometimes uses metric prefixes correctly, sometimes with rounding, e.g., 65 kilowords (KW) meaning for 65536 words, and sometimes uses them incorrectly, with kilowords (KW) meaning 1024 words (2¹⁰) and megawords (MW) meaning 1,048,576 words (2²⁰). With standardization on 8-bit bytes and byte addressability, stating memory sizes in bytes, kilobytes, and megabytes with powers of 1024 rather than 1000 has become the norm, although there is some use of the IEC binary prefixes.

Several of the earliest computers (and a few modern as well) use binary-coded decimal rather than plain binary, typically having a word size of 10 or 12 decimal digits, and some early decimal computers have no fixed word length at all. Early binary systems tended to use word lengths that were some multiple of 6-bits, with the 36-bit word being especially common on mainframe computers. The introduction of ASCII led to the move to systems with word lengths that were a multiple of 8-bits, with 16-bit machines being popular in the 1970s before the move to modern processors with 32 or 64 bits. Special-purpose designs like digital signal processors, may have any word length from 4 to 80 bits.

The size of a word can sometimes differ from the expected due to backward compatibility with earlier computers. If multiple compatible variations or a family of processors share a common architecture and instruction set but differ in their word sizes, their documentation and software may become notationally complex to accommodate the difference (see Size families below).

Uses of words

Depending on how a computer is organized, word-size units may be used for:

Fixed-point numbers: Holders for fixed point, usually integer, numerical values may be available in one or in several different sizes, but one of the sizes available will almost always be the word. The other sizes, if any, are likely to be multiples or fractions of the word size. The smaller sizes are normally used only for efficient use of memory; when loaded into the processor, their values usually go into a larger, word sized holder.

Floating-point numbers: Holders for floating-point numerical values are typically either a word or a multiple of a word.

Addresses: Holders for memory addresses must be of a size capable of expressing the needed range of values but not be excessively large, so often the size used is the word though it can also be a multiple or fraction of the word size.

Registers: Processor registers are designed with a size appropriate for the type of data they hold, e.g. integers, floating-point numbers, or addresses. Many computer architectures use general-purpose registers that are capable of storing data in multiple representations.

Memory–processor transfer: When the processor reads from the memory subsystem into a register or writes a register’s value to memory, the amount of data transferred is often a word. Historically, this amount of bits which could be transferred in one cycle was also called a catena in some environments (such as the Bull). In simple memory subsystems, the word is transferred over the memory data bus, which typically has a width of a word or half-word. In memory subsystems that use caches, the word-sized transfer is the one between the processor and the first level of cache; at lower levels of the memory hierarchy larger transfers (which are a multiple of the word size) are normally used.

Unit of address resolution: In a given architecture, successive address values designate successive units of memory; this unit is the unit of address resolution. In most computers, the unit is either a character (e.g. a byte) or a word. (A few computers have used bit resolution.) If the unit is a word, then a larger amount of memory can be accessed using an address of a given size at the cost of added complexity to access individual characters. On the other hand, if the unit is a byte, then individual characters can be addressed (i.e. selected during the memory operation).

Instructions: Machine instructions are normally the size of the architecture’s word, such as in RISC architectures, or a multiple of the «char» size that is a fraction of it. This is a natural choice since instructions and data usually share the same memory subsystem. In Harvard architectures the word sizes of instructions and data need not be related, as instructions and data are stored in different memories; for example, the processor in the 1ESS electronic telephone switch has 37-bit instructions and 23-bit data words.

Word size choice

When a computer architecture is designed, the choice of a word size is of substantial importance. There are design considerations which encourage particular bit-group sizes for particular uses (e.g. for addresses), and these considerations point to different sizes for different uses. However, considerations of economy in design strongly push for one size, or a very few sizes related by multiples or fractions (submultiples) to a primary size. That preferred size becomes the word size of the architecture.

Character size was in the past (pre-variable-sized character encoding) one of the influences on unit of address resolution and the choice of word size. Before the mid-1960s, characters were most often stored in six bits; this allowed no more than 64 characters, so the alphabet was limited to upper case. Since it is efficient in time and space to have the word size be a multiple of the character size, word sizes in this period were usually multiples of 6 bits (in binary machines). A common choice then was the 36-bit word, which is also a good size for the numeric properties of a floating point format.

After the introduction of the IBM System/360 design, which uses eight-bit characters and supports lower-case letters, the standard size of a character (or more accurately, a byte) becomes eight bits. Word sizes thereafter are naturally multiples of eight bits, with 16, 32, and 64 bits being commonly used.

Variable-word architectures

Early machine designs included some that used what is often termed a variable word length. In this type of organization, an operand has no fixed length. Depending on the machine and the instruction, the length might be denoted by a count field, by a delimiting character, or by an additional bit called, e.g., flag, or word mark. Such machines often use binary-coded decimal in 4-bit digits, or in 6-bit characters, for numbers. This class of machines includes the IBM 702, IBM 705, IBM 7080, IBM 7010, UNIVAC 1050, IBM 1401, IBM 1620, and RCA 301.

Most of these machines work on one unit of memory at a time and since each instruction or datum is several units long, each instruction takes several cycles just to access memory. These machines are often quite slow because of this. For example, instruction fetches on an IBM 1620 Model I take 8 cycles (160 μs) just to read the 12 digits of the instruction (the Model II reduced this to 6 cycles, or 4 cycles if the instruction did not need both address fields). Instruction execution takes a variable number of cycles, depending on the size of the operands.

Word, bit and byte addressing

See main article: word addressing and byte addressing. The memory model of an architecture is strongly influenced by the word size. In particular, the resolution of a memory address, that is, the smallest unit that can be designated by an address, has often been chosen to be the word. In this approach, the word-addressable machine approach, address values which differ by one designate adjacent memory words. This is natural in machines which deal almost always in word (or multiple-word) units, and has the advantage of allowing instructions to use minimally sized fields to contain addresses, which can permit a smaller instruction size or a larger variety of instructions.

When byte processing is to be a significant part of the workload, it is usually more advantageous to use the byte, rather than the word, as the unit of address resolution. Address values which differ by one designate adjacent bytes in memory. This allows an arbitrary character within a character string to be addressed straightforwardly. A word can still be addressed, but the address to be used requires a few more bits than the word-resolution alternative. The word size needs to be an integer multiple of the character size in this organization. This addressing approach was used in the IBM 360, and has been the most common approach in machines designed since then.

When the workload involves processing fields of different sizes, it can be advantageous to address to the bit. Machines with bit addressing may have some instructions that use a programmer-defined byte size and other instructions that operate on fixed data sizes. As an example, on the IBM 7030^[1] («Stretch»), a floating point instruction can only address words while an integer arithmetic instruction can specify a field length of 1-64 bits, a byte size of 1-8 bits and an accumulator offset of 0-127 bits.

In a byte-addressable machine with storage-to-storage (SS) instructions, there are typically move instructions to copy one or multiple bytes from one arbitrary location to another. In a byte-oriented (byte-addressable) machine without SS instructions, moving a single byte from one arbitrary location to another is typically:

1. LOAD the source byte
2. STORE the result back in the target byte

Individual bytes can be accessed on a word-oriented machine in one of two ways. Bytes can be manipulated by a combination of shift and mask operations in registers. Moving a single byte from one arbitrary location to another may require the equivalent of the following:

1. LOAD the word containing the source byte
2. SHIFT the source word to align the desired byte to the correct position in the target word
3. AND the source word with a mask to zero out all but the desired bits
4. LOAD the word containing the target byte
5. AND the target word with a mask to zero out the target byte
6. OR the registers containing the source and target words to insert the source byte
7. STORE the result back in the target location

Alternatively many word-oriented machines implement byte operations with instructions using special byte pointers in registers or memory. For example, the PDP-10 byte pointer contained the size of the byte in bits (allowing different-sized bytes to be accessed), the bit position of the byte within the word, and the word address of the data. Instructions could automatically adjust the pointer to the next byte on, for example, load and deposit (store) operations.

Powers of two

Different amounts of memory are used to store data values with different degrees of precision. The commonly used sizes are usually a power of two multiple of the unit of address resolution (byte or word). Converting the index of an item in an array into the memory address offset of the item then requires only a shift operation rather than a multiplication. In some cases this relationship can also avoid the use of division operations. As a result, most modern computer designs have word sizes (and other operand sizes) that are a power of two times the size of a byte.

Size families

As computer designs have grown more complex, the central importance of a single word size to an architecture has decreased. Although more capable hardware can use a wider variety of sizes of data, market forces exert pressure to maintain backward compatibility while extending processor capability. As a result, what might have been the central word size in a fresh design has to coexist as an alternative size to the original word size in a backward compatible design. The original word size remains available in future designs, forming the basis of a size family.

In the mid-1970s, DEC designed the VAX to be a 32-bit successor of the 16-bit PDP-11. They used word for a 16-bit quantity, while longword referred to a 32-bit quantity; this terminology is the same as the terminology used for the PDP-11. This was in contrast to earlier machines, where the natural unit of addressing memory would be called a word, while a quantity that is one half a word would be called a halfword. In fitting with this scheme, a VAX quadword is 64 bits. They continued this 16-bit word/32-bit longword/64-bit quadword terminology with the 64-bit Alpha.

Another example is the x86 family, of which processors of three different word lengths (16-bit, later 32- and 64-bit) have been released, while word continues to designate a 16-bit quantity. As software is routinely ported from one word-length to the next, some APIs and documentation define or refer to an older (and thus shorter) word-length than the full word length on the CPU that software may be compiled for. Also, similar to how bytes are used for small numbers in many programs, a shorter word (16 or 32 bits) may be used in contexts where the range of a wider word is not needed (especially where this can save considerable stack space or cache memory space). For example, Microsoft’s Windows API maintains the programming language definition of WORD as 16 bits, despite the fact that the API may be used on a 32- or 64-bit x86 processor, where the standard word size would be 32 or 64 bits, respectively. Data structures containing such different sized words refer to them as:

• WORD (16 bits/2 bytes)
• DWORD (32 bits/4 bytes)
• QWORD (64 bits/8 bytes)

A similar phenomenon has developed in Intel’s x86 assembly language – because of the support for various sizes (and backward compatibility) in the instruction set, some instruction mnemonics carry «d» or «q» identifiers denoting «double-«, «quad-» or «double-quad-«, which are in terms of the architecture’s original 16-bit word size.

An example with a different word size is the IBM System/360 family. In the System/360 architecture, System/370 architecture and System/390 architecture, there are 8-bit bytes, 16-bit halfwords, 32-bit words and 64-bit doublewords. The z/Architecture, which is the 64-bit member of that architecture family, continues to refer to 16-bit halfwords, 32-bit words, and 64-bit doublewords, and additionally features 128-bit quadwords.

In general, new processors must use the same data word lengths and virtual address widths as an older processor to have binary compatibility with that older processor.

Often carefully written source code  — written with source-code compatibility and software portability in mind  — can be recompiled to run on a variety of processors, even ones with different data word lengths or different address widths or both.

Table of word sizes

See also

• Integer (computer science)

Notes and References

1. Reference Manual 7030 Data Processing System . August 1961 . Format . http://bitsavers.org/pdf/ibm/7030/22-6530-2_7030RefMan.pdf#page=59 . 50-57 . December 15, 2021 . IBM .
2. Intel Itanium Architecture Software Developer’s Manual . 3: Intel Itanium Instruction Set Reference . 4. Instruction Formats . https://www.intel.com/content/dam/www/public/us/en/documents/manuals/itanium-architecture-vol-3-manual.pdf#page=302 . 3:293 . Three instructions are grouped together into 128-bit sized and aligned containers called bundles. Each bundle contains three 41-bit instruction slots and a 5-bit template field. . April 25, 2022 .